RT600 datasheet(25/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

25 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

PIO0_28

D11

Z I/O 0

PIO0_28 — General-purpose digital input/output pin.

I/O 1

FC4_SCK — Flexcomm 4: USART, SPI, or I2S clock.

R — Reserved.

CTIMER4_MAT0 — 32-bit CTimer4 match output 0.

I2S_BRIDGE_CLK_OUT — Allows I2S bypass by re-routing

a pin that includes the I2S_BRIDGE_CLK_IN function to this

pin.

R — Reserved.

I/O 8

SEC_PIO0_28 — Secure GPIO pin.

PIO0_29

B10

Z I/O 0

PIO0_29 — General-purpose digital input/output pin.

I/O 1

FC4_TXD_SCL_MISO_WS — Flexcomm 4: USART

transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S

word select/frame.

R — Reserved.

CTIMER4_MAT1 — 32-bit CTimer4 match output 1.

I2S_BRIDGE_WS_OUT — Allows I2S bypass by re-routing a

pin that includes the I2S_BRIDGE_WS_IN function to this

pin.

R — Reserved.

I/O 8

SEC_PIO0_29 — Secure GPIO pin.

PIO0_30

C11

Z I/O 0

PIO0_30 — General-purpose digital input/output pin.

I/O 1

FC4_RXD_SDA_MOSI_DATA — Flexcomm 4: USART

receiver, I2C data I/O, SPI master-out/slave-in data, I2S data

I/O.

R — Reserved.

CTIMER4_MAT2 — 32-bit CTimer4 match output 2.

I2S_BRIDGE_DATA_OUT — Allows I2S bypass by

re-routing a pin that includes the I2S_BRIDGE_DATA_IN

function to this pin.

R — Reserved.

I/O 8

SEC_PIO0_30 — Secure GPIO pin.

Table 4.

Pin description …continued

Symbol

Description

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