RT600 datasheet(98/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

98 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

13.3 CoreMark data

[1] Clock source IRC. PLL disabled.

[2] Clock source external clock to XTALIN (bypass mode). PLL enabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: IAR C/C++ Compiler for Arm ver 8.32.3, High, Speed, No Size Constraints.

[5] VDD_AO1V8 = VDD1V8 = VDDIO_0/1/2 = VDDA_ADC1V8 = 1.8 V. VDDA_BIAS = VREFP = 1.8 V. USB1_VDD3V3 = 3.3 V.

[6] For SDK version 2.8 and before (SDK Power Library version = 0x020200): The maximum frequency for the specified VDDCORE

voltage is the frequency of the main clock. This is before the CPU CLOCK Divider. The VDDCORE voltage has to be set according to

the chosen main clock frequency. For SDK version 2.8.3 and after (SDK Power Library version = 0x02030): The maximum frequency for

the specified VDDCORE voltage is the frequency of the clock after CPU CLOCK and DSP clock Divider. The VDDCORE voltage has to

be set according to the chosen M33 CPU and DSP CPU clock frequency. Please see Figure 6 “RT600 clock generation”.

[7] 4.5 MB SRAM enabled. All peripheral clocks disabled (set to NONE). All Array Power enabled (PDRUNCFG 1/2 registers). Only SRAM

partition 12 access enabled (SYSCTL0_AHB_SRAM_ACCESS_DISABLE register). SYSCPUAHBCLKDIV = 0x0.

13.4 Power consumption

Table 23. CoreMark score

Tamb = 25C

Parameter

Conditions

Typ [3][4][5]

Unit

ARM Cortex-M33 in active mode, DSP no clock

CoreMark score

CoreMark code executed from SRAM;

CCLK = 12 MHz, VDDCORE = 0.7 V

[1][6][7]

3.87

(Iterations/s) / MHz

CCLK = 48 MHz, VDDCORE = 0.7 V

[1][6][7]

3.87

(Iterations/s) / MHz

CCLK = 60 MHz, VDDCORE = 0.7 V

[1][6][7]

3.87

(Iterations/s) / MHz

CCLK = 80 MHz, VDDCORE = 0.8 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 110 MHz, VDDCORE = 0.8 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 144 MHz, VDDCORE = 0.9 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 180 MHz, VDDCORE = 0.9 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 204 MHz, VDDCORE = 0.9 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 240 MHz, VDDCORE = 1.0 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 270 MHz, VDDCORE = 1.0 V

[2][6][7]

3.87

(Iterations/s) / MHz

CCLK = 300 MHz, VDDCORE = 1.13 V

[2][6][7]

3.87

(Iterations/s) / MHz

Table 24. Static characteristics: Power consumption in active mode

Tamb = -20C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[2][4][5] Max

Unit

Cortex-M33 in Active mode, DSP no clock[1]

IDDVDDCORE

VDDCOREsupply

current

enhanced while (1) code executed

from SRAM; Internal LDO disabled

CCLK = 12 MHz,

VDDCORE = 0.7 V

[3][6][7]

3.0

CCLK = 48 MHz

VDDCORE = 0.7 V

[3][6][7]

6.0

CCLK = 60 MHz

VDDCORE = 0.7 V

[3][6][7]

7.0

CCLK = 80 MHz

VDDCORE = 0.8 V

[6][7][8]

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