RT600 datasheet(101/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

101 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

[1] Based on the power API library from the SDK software package available on nxp.com.

[2] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C). VDD_AO1V8 = VDD1V8 = VDDIO_0/1/2 =

VDDA_ADC1V8 = 1.8 V. VDDA_BIAS = VREFP = 1.8 V. USB1_VDD3V3 = 3.3 V

[3] Clock source IRC. PLL disabled.

[4] Characterized through bench measurements using typical samples.

[5] Compiler settings: Keil Compiler for Arm ver 5.28, optimization level 3

[6] For SDK version 2.8 and before (SDK Power Library version = 0x020200): The maximum frequency for the specified VDDCORE

voltage is the frequency of the main clock. This is before the CPU CLOCK Divider. The VDDCORE voltage has to be set according to

the chosen main clock frequency. For SDK version 2.8.3 and after (SDK Power Library version = 0x02030): The maximum frequency for

the specified VDDCORE voltage is the frequency of the clock after CPU CLOCK and DSP clock Divider. The VDDCORE voltage has to

be set according to the chosen M33 CPU and DSP CPU clock frequency. Please see Figure 6 “RT600 clock generation”.

[7] 4.5 MB SRAM enabled. All peripheral clocks disabled (set to NONE). All Array Power enabled (PDRUNCFG 1/2 registers). Only SRAM

partition 12 access enabled (SYSCTL0_AHB_SRAM_ACCESS_DISABLE register). SYSCPUAHBCLKDIV = 0x0.

[8] Clock source external clock to XTALIN (bypass mode). PLL enabled.

CCLK = 110 MHz

VDDCORE = 0.8 V

[6][7][8]

CCLK = 144 MHz

VDDCORE = 0.8 V

[6][7][8]

CCLK = 180 MHz

VDDCORE = 0.8 V

[6][7][8]

CCLK = 204 MHz

VDDCORE = 0.8 V

[6][7][8]

CCLK = 240 MHz

VDDCORE = 0.9 V

[6][7][8]

CCLK = 270 MHz

VDDCORE = 0.9 V

[6][7][8]

CCLK = 300 MHz

VDDCORE = 0.9 V

[6][7][8]

CCLK = 400 MHz

VDDCORE = 1.0 V

[6][7][8]

117

CCLK = 600 MHz

VDDCORE = 1.13 V

[6][7][8]

207

Table 26. Static characteristics: Power consumption in active mode …continued

Tamb = -20C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[2][4][5] Max

Unit

Table 27. Static characteristics: Power consumption in sleep mode

Tamb = -20 C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

Cortex-M33 in Sleep mode, DSP no clock

IDDVDDCORE VDDCORE supply current

CCLK = 12 MHz

VDDCORE = 0.7 V [1][2][3][4][5][6] -

CCLK = 48 MHz

VDDCORE = 0.7 V [1][2][3][4][5][6] -

CCLK = 250 MHz

VDDCORE = 1.0 V

[1][2][3][4][5][7] -

20.3

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