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RT600 Datasheet(PDF) 29 Page - NXP Semiconductors

Part # RT600
Description  Dual-core microcontroller with 32-bit Cortex®-M33 and Xtensa HiFi4 Audio DSP CPUs; Up to 4.5 MB SRAM; FlexSPI with cache and dynamic decryption; High-speed USB device/host
PDF  171 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

RT600 Datasheet(HTML) 29 Page - NXP Semiconductors

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RT600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2023. All rights reserved.
Product data sheet
Rev. 2.1 — 7 July 2023
29 of 173
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
PIO1_15
C2
N3
M15
Z I/O 0
PIO1_15 — General-purpose digital input/output pin.
Remark: The state of this pin at Reset in conjunction with
PIO1_16 and PIO1_17 will determine the boot source for the
part or if ISP handler is invoked. See the Boot Process
chapter in the relevant User Manual for more details.
I/O 1
HS_SPI_SSEL1 — Slave Select 1 for high speed SPI.
2
R — Reserved
3
R — Reserved
O
4
CTIMER3_MAT0 — 32-bit CTimer3 match output 0.
PIO1_16
C3
M4
P17
Z I/O 0
PIO1_16 — General-purpose digital input/output pin.
Remark: The state of this pin at Reset in conjunction with
PIO1_15 and PIO1_17 will determine the boot source for the
part or if ISP handler is invoked. See the Boot Process
chapter in the relevant User Manual for more details.
I/O 1
HS_SPI_SSEL2 — Slave Select 2 for high speed SPI.
O
2
SCT0_OUT8 — SCTimer/PWM output 8.
3
R — Reserved.
O
4
CTIMER3_MAT1 — 32-bit CTimer3 match output 1.
PIO1_17
B2
N4
M13
Z I/O 0
PIO1_17 — General-purpose digital input/output pin.
Remark: The state of this pin at Reset in conjunction with
PIO1_15 and PIO1_16 will determine the boot source for the
part or if ISP handler is invoked. See the Boot Process
chapter in the relevant User Manual for more details.
I/O 1
HS_SPI_SSEL3 — Slave Select 3 for high speed SPI.
O
2
SCT0_OUT9 — SCTimer/PWM output 9.
3
R — Reserved.
O
4
CTIMER3_MAT2 — 32-bit CTimer3 match output 2.
PIO1_18
B7
T9
U4
Z I/O 0
PIO1_18 — General-purpose digital input/output pin.
O
1
FLEXSPI0A_SCLK — Clock output for the FlexSPI A
interface.
I
2
SCT0_GPI0 — Pin input 0 to SCTimer/PWM.
3
R — Reserved.
O
4
CTIMER3_MAT3 — 32-bit CTimer3 match output 3.
PIO1_19
B4
T4
U16
Z I/O 0
PIO1_19 — General-purpose digital input/output pin.
O
1
FLEXSPI0A_SS0_N — Active low slave select 0 for the
FlexSPI A interface.
O
2
SCT0_OUT0 — SCTimer/PWM output 0.
3
R — Reserved.
O
4
CTIMER4_MAT0 — 32-bit CTimer4 match output 0.
Table 4.
Pin description …continued
Symbol
Description



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