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RT600 Datasheet(PDF) 35 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 35 Page - NXP Semiconductors |
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35 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 7 July 2023 35 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs PIO2_21 A3 R3 P13 Z I/O 0 PIO2_21 — General-purpose digital input/output pin. I 1 PDM_DATA23 — PDM data input for DMIC channels 2 and 3. 2 R — Reserved. 3 R — Reserved. I 4 CTIMER_INP14 — Capture input 14 to CTIMER input muxes. 5 R — Reserved. O 6 FLEXSPI0B_SS1_N — Active low slave select 1 for the FlexSPI B interface. PIO2_22 - P3 P14 Z I/O 0 PIO2_22 — General-purpose digital input/output pin. I 1 PDM_DATA45 — PDM data input for DMIC channels 4 and 5. 2 R — Reserved. 3 R — Reserved. 4 R — Reserved. 5 R — Reserved. I/O 6 FLEXSPI0B_DATA6 — Data bit 6 for the FlexSPI B interface. PIO2_23 - P5 R14 Z I/O 0 PIO2_23 — General-purpose digital input/output pin. I 1 PDM_DATA67 — PDM data input for DMIC channels 6 and 7. 2 R — Reserved. 3 R — Reserved. 4 R — Reserved. 5 R — Reserved. I/O 6 FLEXSPI0B_DATA7 — Data bit 7 for the FlexSPI B interface. PIO2_24 - L16 G2 Z I/O 0 PIO2_24 — General-purpose digital input/output pin. O 1 SWO — Serial Wire Debug trace output. 2 R — Reserved. 3 R — Reserved. 4 R — Reserved. 5 R — Reserved. O 6 GPIO_INT_BMAT — Output of the pin interrupt pattern match engine. PIO2_25 D8 L17 F1 Z I/O 0 PIO2_25 — General-purpose digital input/output pin. O 1 SWCLK — Serial Wire Debug clock. This is the default function after booting. Since the internal pull-ups are disabled by default, connect external pull-up or pull-down resistor (~10 Kohm) on SWCLK pin to comply with the ARM SWD interface spec. Table 4. Pin description …continued Symbol Description |
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