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RT600 Datasheet(PDF) 60 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 60 Page - NXP Semiconductors |
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60 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 7 July 2023 60 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 10.12.7 Shared RAM detail Table 11 reflects both the Cortex-M33 and DSP views of the RAM partitions and address. The AHB matrix port is only relevant to the Cortex-M33 because the DSP accesses these RAMs via a separate bus. The partitions shown in Table 11 are mirrored in all four shared RAM address regions for the Cortex-M33. The purpose of those regions is outlined in Section 10.12.3, while Table 12 gives the base addresses for the four regions. A variety of shared RAM partition sizes are provided to allow more flexibility in assigning the uses of those spaces. For each application, shard RAM usage should be planned to minimize collision of accesses by the two buses of the Cortex-M33, as well as other bus masters, including DMA controllers and the HiFi 4. A best case would be if each shared RAM partition is accessed by only one master at any particular time, “ownership” being passed to another master (for instance) when a buffer is filled from a peripheral, a block of data is processed by an algorithm, etc. To summarize, access collisions can occur under the following conditions. • On the AHB matrix: when two AHB masters access a resource on the same slave port at the same time. AHB masters include the HiFi 4 when it is using the AHB matrix, not when it is accessing shared RAM. • HiFi 4 accessing shared RAM: when the HiFi 4 and an AHB master access the same shared RAM partition at the same time. Note that in this case, the access collision happens at the partition, not at the slave port. Since there are multiple partitions for each slave port, this allows even more opportunity to avoid collisions. Table 11. Shared RAM memory map: offsets for all types of shared memory accesses AHB port Partition Start offset End offset Size 2 0 0x00 0000 0x00 7FFF 32 KB 1 0x00 8000 0x00 FFFF 32 KB 3 2 0x01 0000 0x01 7FFF 32 KB 3 0x01 8000 0x01 FFFF 32 KB 4 4 0x02 0000 0x02 7FFF 32 KB 5 0x02 8000 0x02 FFFF 32 KB 6 0x03 0000 0x03 7FFF 32 KB 7 0x03 8000 0x03 FFFF 32 KB 5 8 0x04 0000 0x04 FFFF 64 KB 9 0x05 0000 0x05 FFFF 64 KB 10 0x06 0000 0x06 FFFF 64 KB 11 0x07 0000 0x07 FFFF 64 KB 6 12 0x08 0000 0x09 FFFF 128 KB 13 0x0A 0000 0x0B FFFF 128 KB 14 0x0C 0000 0x0D FFFF 128 KB 15 0x0E 0000 0x0F FFFF 128 KB |
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