RT600 datasheet(55/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

55 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

The MPU register interface is located on the private peripheral bus and is described in

detail in Cortex-M33 DGUG — ARM Cortex-M33 Devices Generic User Guide

10.12.3 TrustZone and Cortex-M33 busing on this device

The implementation of ARM TrustZone on this device involves using address bit 28 to

divide the address space into potential secure and non-secure regions. Address bit 28 is

not decoded in memory access hardware, so each physical location appears in two

places on whatever bus they are located on. Other hardware determines which kinds of

accesses (including non-secure callable) are actually allowed for any particular address.

In addition, the shared RAM is generally expected to be used for both code and data, in

different balance for different applications. Some applications may require a great deal of

code and little data, others may require most of the shared RAM to be used for data. For

this reason, the entire shared RAM appears on both the code bus and the data bus of the

Cortex-M33. Code can be located at addresses that are on the code bus, data can be

located at addresses that are on the data bus. As long as code and data are contained in

shared RAM that is connected on different AHB matrix slave ports, each can be accessed

simultaneously on the appropriate bus.

Table 8 shows the overall mapping of the code and data buses for secure and non-secure

accesses to various device resources. The block diagrams in Figure 3 “Block diagram

overview” may also be useful in understanding the memory map.

In addition to the fixed mapping of secure and non-secure spaces, “checker” hardware

present on all AHB matrix ports confirms the types of access allowed for each peripheral

or memory range (with a granularity of 32 memory ranges for each port). This is described

in more detail in RT6xx User Manual (please see RT6xx Trusted execution environment

chapter)

Remark: In the peripheral description chapters of this manual, only the native

(non-secure) base address is noted, secure base addresses can be found in this chapter

or created algorithmically where needed.

[1] The HiFi 4 accesses shared RAM via a separate connection, not using the AHB matrix.

[2] The size shown for peripherals spaces indicates the space allocated in the memory map, not the actual

space used by the peripheral.

[3] Some AHB and APB peripherals are not accessible to the HiFi 4.

[4] Selected areas of secure regions may be marked as non-secure callable.

10.12.4 Links to specific memory map descriptions and tables:

• Section 10.12.5 “Device overview”

Table 8.

TrustZone and Cortex-M33 general mapping

Start address End address TrustZone CM-33 bus CM-33 usage

0x0000 0000 0x0FFF FFFF Non-secure Code

Shared RAM, Boot ROM, OSPI memory mapped region.

0x1000 0000 0x1FFF FFFF Secure

Code

Same as above

0x2000 0000 0x2FFF FFFF Non-secure Data

Shared RAM, CM33 access to HiFi 4 TCMs via inbound PIF.

Non-cacheable FlexSPI memory mapped region for DSP only.

0x3000 0000 0x3FFF FFFF Secure

Data

Same as above

0x4000 0000 0x4FFF FFFF Non-secure Data

AHB and APB peripherals.

0x5000 0000 0x5FFF FFFF Secure

Data

Same as above

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