RT600 datasheet(57/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.1 — 7 July 2023

57 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

10.12.5 Device overview

The RT600 incorporates several distinct memory regions. Table 9 gives a simplified view

of the overall map of the entire address space from the user program viewpoint following

reset. The figure indicates the main address regions and how (or whether) they related to

both the Cortex-M33 and the HiFi 4.

[1] The HiFi 4 accesses shared RAM via a separate connection, not using the AHB matrix.

[2] Access to the FlexSPI memory space can be enabled or disabled for the CM33 and the HiFi 4.

Table 9.

Device overview memory map

Start addr

End addr

Size

Cortex-M33 function

HiFi 4 function

0x0000 0000 0x0047 FFFF 4.5 MB Shared RAM via the CM33 code bus (non-secure

access). See Section 10.12.7.

Shared RAM - cacheable

access. See Section 10.12.10.

[1]

0x0300 0000 0x0303 FFFF 256 KB Boot ROM (non-secure access). See

Section 10.12.6

0x0800 0000 0x0FFF FFFF 128 MB FlexSPI memory mapped space with cache and

on-the-fly AES decryption (non-secure access).

See Section 10.12.6. [2]

FlexSPI memory mapped

space, cacheable. See

Section 10.12.10. [2]

0x1000 0000 0x1047 FFFF 4.5 MB Shared RAM via the CM33 code bus (secure

access). See Section 10.12.7. [3]

0x1300 0000 0x1303 FFFF 256 KB Boot ROM (secure access). See Section 10.12.6

0x1800 0000 0x1FFF FFFF 128 MB FlexSPI memory mapped space with cache and

on-the-fly AES decryption (secure access). See

Section 10.12.6.

0x2000 0000 0x2047 FFFF 4.5 MB Shared RAM via the CM33 data bus (non-secure

access). See Section 10.12.7.

Shared RAM - non-cacheable

access. See Section 10.12.10.

[1]

0x2400 0000 0x2400 FFFF 64 KB

Cortex-M33 access to HiFi 4 data TCM via inbound

PIF (non-secure access). See Section 10.12.6.

HiFi 4 data TCM - 4

interleaved banks. See

Section 10.12.10.

0x2402 0000 0x2402 FFFF 64 KB

Cortex-M33 access to HiFi 4 instruction TCM via

inbound PIF (non-secure access). See

Section 10.12.6.

HiFi 4 instruction TCM. See

Section 10.12.10.

0x2800 0000 0x2FFF FFFF 128 MB -

FlexSPI memory mapped

space, non-cacheable. See

Section 10.12.10. [2]

0x3000 0000 0x3047 FFFF 4.5 MB Shared RAM via the CM33 data bus (secure

access). See Section 10.12.7. [3]

0x3400 0000 0x3400 FFFF 64 KB

Cortex-M33 access to HiFi 4 data TCM via inbound

PIF (secure access). See Section 10.12.6.

0x3402 0000 0x3402 FFFF 64 KB

Cortex-M33 access to HiFi 4 instruction TCM via

inbound PIF (secure access). See Section 10.12.6.

HiFi 4 instruction TCM. See

Section 10.12.10.

0x4000 0000 0x4003 FFFF 256 KB

[4]

APB peripherals (non-secure access). See

Section 10.12.8.

APB peripherals. See

Section 10.12.10. [5]

0x4010 0000 0x4015 FFFF 400 KB

[4]

AHB peripherals (non-secure access). See

Section 10.12.9.

AHB peripherals. See

Section 10.12.10. [5]

0x5000 0000 0x5003 FFFF 256 KB

[4]

APB peripherals (secure access). See

Section 10.12.8.

0x5010 0000 0x5015 FFFF 400 KB

[4]

AHB peripherals (secure access). See

Section 10.12.9.

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