TMPR4925 datasheet(571/590 Pages) TOSHIBA

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Chapter 22 Electrical Characteristics

22-5

22.5.3

SDRAM Interface AC Characteristics

(Tc = 0 ~ 70

°C, VCCIO = 3.3 V ± 0.3 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V, CL = 50 pF)

Parameter

Symbol

Rating

Min.

Max.

Unit

SDCLK[3:0] Cycle Time

tCYC_SDCLK

12.5



SDCLK[3:0] High Time

tHIGH_SDCLK



SDCLK[3:0] Low Time

tLOW_SDCLK



SDCLKIN Skew

tBP

Non bypass mode

4.0

ADDR[19:16,14:5],SADDR10 Output delay

tVAL_ADDR1

(*1)

1.5

7.5

SDCS[3:0]* Output delay

tVAL_SDCS

1.5

7.5

RAS* Output delay

tVAL_RAS

(*1)

1.5

7.5

CAS* Output delay

tVAL_CAS

(*3)

1.5

7.5

WE* Output delay

tVAL_WE

(*3)

1.5

7.5

CKE Output delay

tVAL_CKE

1.5

7.5

DQM[3:0] Output delay

tVAL_DQM

(*2)

1.5

7.5

DATA[31:0] Output delay (H->L, L->H)

tVAL_DATA1

(*2)

1.5

7.5

DATA[31:0] Output delay (High-Z->Valid)

tVAL_DATA1ZV

(*2)

1.5

7.5

DATA[31:0] Output delay (Valid->High-Z)

tVAL_DATA1VZ

(*2)

1.5

7.5

DATA[31:0] Input set-up time

tSU_DATA1B

Bypass mode

6.0



DATA[31:0] input hold time

tHO_DATA1B

Bypass mode

0.5



DATA[31:0] Input set-up time

tSU_DATA1NB

Non bypass mode

1.0



DATA[31:0] input hold time

tHO_DATA1NB

Non bypass mode

2.0



*1:

An SDRAM bus transaction can complete in no more than two clock cycles when the SDCTR.DA is set to 1.

*2:

An SDRAM bus transaction can complete in no more than two clock cycles when the SDCTR.SWB is set to 1.

*3:

2 cycle signals.

Figure 22.5.3 Timing Diagrams: Output Signals and When Bypass Mode Input Signals (SDCLK Basis)

Figure 22.5.4 Timing Diagrams: When Non Bypass Mode Input Signals (SDCLK Basis)

SDCLK[n]

tSU_*

tHO_*

outputs valid

inputs valid

tVAL_*

OUTPUT

INPUT

tSU_*

tHO_*

SDCLK[n]

tBP

inputs valid

SDCLKIN

INPUT

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