UPD17231 datasheet(33/94 Pages) RENESAS

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Data Sheet U14360EJ1V0DS00

µPD17230, 17231, 17232, 17233, 17234, 17235, 17236

3.7

INT Pin

This pin inputs an external interrupt request signal. At either the rising or falling edge of the signal input to this

pin, the IRQ flag (RF: address 3EH, bit 0) is set.

The status of this pin can be read by using the INT flag (RF: address 0FH, bit 0). When the high level is input to

the pin, the INT flag is set to “1”; when the low level is input, the flag is reset to “0” (refer to 7.2.1 INT).

Figure 3-1.

Relations between Port Register and Each Pin

Bank Address

Target Port

Bit

Output

Read Contents

Written Contents

On Reset

Format

Input mode Output mode Input mode Output mode

70H

Port 0A

P0A3

Input

Pin status

–

Input mode

P0A2

(with pull-up

P0A1

resistor)

P0A0

71H

Port 0B

P0B3

N-ch

Output latch Output latch Output latch

P0B2

open drain

P0B1

P0B0

72H

Port 0C

P0C3

Output mode

P0C2

(low-level

P0C1

output)

P0C0

73H

Port 0D

P0D3

P0D2

P0D1

P0D0

6FH

Port 0E

P0E3

CMOS

Input mode

P0E2

push-pull

(without pull-

P0E1

up resistor)

P0E0

70H

Port 1A

P1A0

Input

–

Input mode

(input/output

(in input

(without pull-

mode set by

mode)

up resistor)

mask option)

N-ch

–

Output latch

Output latch Output latch Output mode

open drain

(high-

(in output

impedance

mode)

output)

UPD17231 Datasheet(PDF) 33 Page - Renesas Technology Corp

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