UPD17231 datasheet(55/94 Pages) RENESAS

55 / 94 page

Data Sheet U14360EJ1V0DS00

µPD17230, 17231, 17232, 17233, 17234, 17235, 17236

7.3

Interrupt Sequence

If IRQ

×× flag is set to “1” when IP×× flag is “1”, interrupt processing is started after the instruction cycle of the

instruction executed when IRQ

×× flag was set has ended. Since the MOVT instruction, EI instruction, and the

instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction

is executed is processed after the second instruction cycle is over.

If IP

×× flag is “0”, the interrupt processing is not performed even if IRQ×× flag is set, until IP×× flag is set.

If two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the

highest priority. The interrupt with the lower priority is kept pending until the processing of the interrupt with the higher

priority is finished.

7.3.1

Operations when interrupt is accepted

When an interrupt has been accepted, the CPU performs processing in the following sequence:

Clears IRQ

corresponding to

INTE flag and accepted interrupt

×××

Decrements value of stack pointer by 1

(SP – 1)

Saves contents of program counter to

stack addressed by stack pointer

Loads vector address to program counter

Save contents of PSWORD to interrupt stack register

One instruction cycle is required to perform the above processing.

UPD17231 Datasheet(PDF) 55 Page - Renesas Technology Corp