UPD17231 datasheet(79/94 Pages) RENESAS

79 / 94 page

Data Sheet U14360EJ1V0DS00

µPD17230, 17231, 17232, 17233, 17234, 17235, 17236

System Clock Oscillator Characteristics (TA = –40 to +85

°C, VDD = 2.0 to 3.6 V)

Resonator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation frequency

1.0

4.0

8.0

MHz

resonator

(fX)Note 1

Oscillation

After VDD reached MIN.

stabilization timeNote 2

in oscillation voltage

range

Notes 1. The oscillation frequency only indicates the oscillator characteristics.

2. The oscillation stabilization time is necessary for oscillation to be stabilized, after VDD application or

STOP mode release.

Caution To use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted

line in the above figure as follows, to avoid adverse wiring capacitance influences:

•

Keep wiring length as short as possible.

•

Do not cross a signal line with some other signal lines. Do not route the wiring in the vicinity

of lines through which a large current flows.

•

Always keep the oscillator circuit capacitor ground at the same potential as GND. Do not

ground the capacitor to a ground pattern, through which a large current flows.

•

Do not extract signals from the oscillator circuit.

External circuit example

X IN

X OUT

XIN

XOUT

UPD17231 Datasheet(PDF) 79 Page - Renesas Technology Corp

UPD17231 Datasheet(HTML) 79 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL