UPD17231 datasheet(28/94 Pages) RENESAS

28 / 94 page

Data Sheet U14360EJ1V0DS00

µPD17230, 17231, 17232, 17233, 17234, 17235, 17236

2.5

The register file mainly consists of registers that set the conditions of the peripheral hardware.

These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro

instructions of RA17K, SETn, CLRn, and INITFLG.

2.5.1

Configuration of register file

Figure 2-10 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE

instructions.

The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers

are assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data

memory cannot be accessed when the PEEK or POKE instruction is used.

The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control

registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses.

The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging.

Figure 2-10. Register File Access with PEEK or POKE Instructions

0123456789

Column address

Data memory

System register

PEEK WR, SP

POKE LCDMD, WR

POKE M063, WR

Control register

UPD17231 Datasheet(PDF) 28 Page - Renesas Technology Corp