ATMEGA640 datasheet(151/449 Pages) ATMEL

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ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double

buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle

its logical level on each compare match by setting the Compare Output mode bits to tog-

gle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the

data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will

have a maximum frequency of f

OCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The

waveform frequency is defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x0000.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) pro-

vides a high frequency PWM waveform generation option. The fast PWM differs from

the other PWM options by its single-slope operation. The counter counts from BOTTOM

to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output

Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx, and

set at BOTTOM. In inverting Compare Output mode output is set on compare match and

cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the

fast PWM mode can be twice as high as the phase correct and phase and frequency

correct PWM modes that use dual-slope operation. This high frequency makes the fast

PWM mode well suited for power regulation, rectification, and DAC applications. High

frequency allows physically small sized external components (coils, capacitors), hence

reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in

ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then

cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is

shown in Figure 54. The figure shows fast PWM mode when OCRnA or ICRn is used to

define TOP. The TCNTn value is in the timing diagram shown as a histogram for illus-

trating the single-slope operation. The diagram includes non-inverted and inverted PWM

outputs. The small horizontal line marks on the TCNTn slopes represent compare

matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a com-

pare match occurs.

OCnA

clk_I/O

2 N

OCRnA

()

⋅⋅

---------------------------------------------------

FPWM

TOP

()

log

()

log

-----------------------------------

ATMEGA640 Datasheet(PDF) 151 Page - ATMEL Corporation

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