ATMEGA640 datasheet(156/449 Pages) ATMEL

156 / 449 page

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ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Figure 56. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the

OCRnx Registers are updated with the double buffer value (at BOTTOM). When either

OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag set when

TCNTn has reached TOP. The Interrupt Flags can then be used to generate an interrupt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNTn and the OCRnx.

As Figure 56 shows the output generated is, in contrast to the phase correct mode, sym-

metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COMnx1:0 to three (See Table 85 on page 161). The actual OCnx value will only be vis-

ible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The

PWM waveform is generated by setting (or clearing) the OCnx Register at the compare

match between OCRnx and TCNTn when the counter increments, and clearing (or set-

ting) the OCnx Register at compare match between OCRnx and TCNTn when the

counter decrements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnxPFCPWM

clk_I/O

2 NTOP

⋅⋅

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ATMEGA640 Datasheet(PDF) 156 Page - ATMEL Corporation

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