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ATMEGA640 Datasheet(PDF) 157 Page - ATMEL Corporation |
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ATMEGA640 Datasheet(HTML) 157 Page - ATMEL Corporation |
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157 / 449 page ![]() 157 ATmega640/1280/1281/2560/2561 2549K–AVR–01/07 The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk Tn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 57 shows a timing diagram for the setting of OCFnx. Figure 57. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling Figure 58 shows the same timing data, but with the prescaler enabled. Figure 58. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk_I/O/8) Figure 59 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by clk Tn (clk I/O/1) OCFnx clk I/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
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