ATMEGA640 datasheet(183/449 Pages) ATMEL

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183

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

At the very start of period 2 in Figure 70 OCnx has a transition from high to low even

though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

•

OCR2A changes its value from MAX, like in Figure 70. When the OCR2A value is

MAX the OCn pin value is the same as the result of a down-counting compare

match. To ensure symmetry around BOTTOM the OCn value at MAX must

correspond to the result of an up-counting Compare Match.

•

The timer starts counting from a value higher than the one in OCR2A, and for that

reason misses the Compare Match and hence the OCn change that would have

happened on the way up.

OCnxPCPWM

clk_I/O

N 510

⋅

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ATMEGA640 Datasheet(PDF) 183 Page - ATMEL Corporation