ATMEGA640 datasheet(184/449 Pages) ATMEL

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ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator

signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the

next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare

Flag generates an Output Compare interrupt. The Output Compare Flag is automatically

cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be

cleared by software by writing a logical one to its I/O bit location. The Waveform Gener-

ator uses the match signal to generate an output according to operating mode set by the

WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom sig-

nals are used by the Waveform Generator for handling the special cases of the extreme

values in some modes of operation (“Modes of Operation” on page 179).

Figure 57 on page 157 shows a block diagram of the Output Compare unit.

Figure 71. Output Compare Unit, Block Diagram

The OCR2x Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,

the double buffering is disabled. The double buffering synchronizes the update of the

OCR2x Compare Register to either top or bottom of the counting sequence. The syn-

chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses,

thereby making the output glitch-free.

The OCR2x Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double

buffering is disabled the CPU will access the OCR2x directly.

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare

match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be

updated as if a real compare match had occurred (the COM2x1:0 bits settings define

whether the OC2x pin is set, cleared or toggled).

Compare Match Blocking by

TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

ATMEGA640 Datasheet(PDF) 184 Page - ATMEL Corporation

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