ATMEGA640 datasheet(186/449 Pages) ATMEL

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186

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as

output before the OC2x value is visible on the pin. The port override function is indepen-

dent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2x state before

the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain

modes of operation. See “Register Description” on page 191.

Compare Output Mode and

Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM

modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no

action on the OC2x Register is to be performed on the next compare match. For com-

pare output actions in the non-PWM modes refer to Table 91 on page 192. For fast

PWM mode, refer to Table 92 on page 192, and for phase correct PWM refer to Table

93 on page 193.

A change of the COM2x1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC2x strobe bits.

Timer/Counter Timing

Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock

(clk

T2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should

be replaced by the Timer/Counter Oscillator clock. The figures include information on

when Interrupt Flags are set. Figure 73 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 73. Timer/Counter Timing Diagram, no Prescaling

Figure 74 shows the same timing data, but with the prescaler enabled.

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

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