ATMEGA640 datasheet(207/449 Pages) ATMEL

207 / 449 page

207

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency f

osc is shown in the following table:

SPSR – SPI Status Register

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if

SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low

when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively, the

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing

the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

• Bit 5:1 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Table 100). This means that the minimum SCK period

will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only

guaranteed to work at f

osc/4 or lower.

The SPI interface on the ATmega640/1280/1281/2560/2561 is also used for program

memory and EEPROM downloading or uploading. See “Serial Downloading” on page

356 for serial programming and verification.

Table 100. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

osc/4

osc/16

osc/64

osc/128

osc/2

osc/8

osc/32

osc/64

Bit

7654

321

0x2D (0x4D)

SPIF

WCOL

–

SPI2X

SPSR

Read/Write

RRRR

R/W

Initial Value

0000

000

ATMEGA640 Datasheet(PDF) 207 Page - ATMEL Corporation

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