ATMEGA640 datasheet(211/449 Pages) ATMEL

211 / 449 page

211

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver.

The USARTn supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn

bit in USART Control and Status Register C (UCSRnC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn =

1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the

clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only

active when using synchronous mode.

Figure 83 shows a block diagram of the clock generation logic.

Figure 83. Clock Generation Logic, Block Diagram

Signal description:

txclk

Transmitter clock (Internal Signal).

rxclk

Receiver base clock (Internal Signal).

xcki

Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

OSC

XTAL pin frequency (System Clock).

Prescaling

Down-Counter

UBRR

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

Detector

UCPOL

ATMEGA640 Datasheet(PDF) 211 Page - ATMEL Corporation

ATMEGA640 Datasheet(HTML) 211 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL