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STPMIC25 Datasheet(PDF) 106 Page - STMicroelectronics |
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STPMIC25 Datasheet(HTML) 106 Page - STMicroelectronics |
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106 / 145 page ![]() 6.6.3 Interrupt pending register 2 (INT_PENDING_R2) Table 72. INT_PENDING_R2 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved THW_RI THW_FA R R R R R R R R • Address: 0x78 • Default: 0x00 • Description: Interrupt pending register 2 (see Section 6.6.1). This register is reset to the default value as long as RSTn is asserted. For all bits: 0: interrupt not pending 1: interrupt pending [7:2] reserved [1] THW_RI: Temperature rises above the TWRN_Rise threshold [0] THW_FA: Temperature fall below the TWRN_Fall threshold 6.6.4 Interrupt pending register 3 (INT_PENDING_R3) Table 73. INT_PENDING_R3 7 6 5 4 3 2 1 0 REFDDR_OCP BUCK7_OCP BUCK6_OCP BUCK5_OCP BUCK4_OCP BUCK3_OCP BUCK2_OCP BUCK1_OCP R R R R R R R R • Address: 0x72 • Default: 0x00 • Description: Interrupt pending register 3 (see Section 6.6.1). This register is reset to the default value as long as RSTn is asserted. For all bits: 0: interrupt not pending 1: interrupt pending [7] REFDDR_OCP: Overcurrent detected on REFDDR [6] BUCK7_OCP: Overcurrent detected on BUCK7 [5] BUCK6_OCP: Overcurrent detected on BUCK6 [4] BUCK5_OCP: Overcurrent detected on BUCK5 [3] BUCK4_OCP: Overcurrent detected on BUCK4 [2] BUCK3_OCP: Overcurrent detected on BUCK3 [1] BUCK2_OCP: Overcurrent detected on BUCK2 [0] BUCK1_OCP: Overcurrent detected on BUCK1 STPMIC25 Register descriptions DS14278 - Rev 3 page 106/145 |
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