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STPMIC25 Datasheet(PDF) 105 Page - STMicroelectronics

Part # STPMIC25
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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STPMIC25 Datasheet(HTML) 105 Page - STMicroelectronics

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6.6
Interrupt registers
6.6.1
Interrupt management overview
Interrupts are probed in the POWER_ON state only. All interrupts are masked by default. All interrupt registers are
reset to the default value as long as RSTn is asserted.
•
INT_PENDING_Rx
–
Stores events of interrupt sources, regardless if the interrupts are masked or not masked.
–
Corresponding bits are kept set until they are cleared (using INT_CLEAR_Rx registers).
•
INT_CLEAR_Rx
–
Setting a bit in these registers clears the corresponding pending bit in the INT_PENDING_Rx
registers. A bit in the INT_PENDING_Rx registers can be cleared only if the corresponding interrupt
source disappears. Alternatively, the bit stays set after being cleared. In the case of the
INT_PENDING_Rx bit generated by edge triggering, they can be directly deleted without checking
the INT_SOURCE_RX.
•
INT_MASK_Rx
–
Clearing a bit in these registers unmasks the corresponding interrupt.
–
The INTn pin is forced low as long as the corresponding interrupt bit is set in INT_PENDING_Rx.
•
INT_SOURCE_Rx
–
These registers provide the actual state of interrupt sources.
–
If an interrupt source is present, the corresponding bit is set. If the interrupt source disappears, the
corresponding bit is cleared.
•
INT_DBG_LATCH_Rx
–
Setting a bit in these registers emulates the corresponding interrupt event. These registers aim to test
and to debug the application processor software interrupt handler.
6.6.2
Interrupt pending register 1 (INT_PENDING_R1)
Table 71. INT_PENDING_R1
7
6
5
4
3
2
1
0
VBUS_RI
VBUS_FA
VINLOW_RI
VINLOW_FA
WKP_RI
WKP_FA
PKEY_RI
PKEY_FA
R
R
R
R
R
R
R
R
•
Address: 0x70
•
Default: 0x00
•
Description: Interrupt pending register 1 (see Section 6.6.1).
This register is reset to the default value as long as RSTn is asserted.
For all bits:
0: interrupt not pending
1: interrupt pending
[7]
VBUS_RI: Voltage on the VBUS pin rises above the VBUS_Rise threshold
[6]
VBUS_FA: Voltage on the VBUS pin falls below the VBUS_Fall threshold
[5]
VINLOW_RI: Voltage on the VIN pin falls below the VINLOW_Rise threshold
[4]
VINLOW_FA: Voltage on the VIN pin rises above the VINLOW_Fall threshold
[3]
WKP_RI: WAKEUP rising edge
[2]
WKP_FA: WAKEUP falling edge
[1]
PKEY_RI: PONKEYn rising edge
[0]
PKEY_FA: PONKEYn falling edge
STPMIC25
Register descriptions
DS14278 - Rev 3
page 105/145



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