STPMIC25 datasheet(108/145 Pages) STMICROELECTRONICS

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6.6.7

Interrupt mask registers (INT_MASK_Rx) (x = 1 to 4)

Table 76. INT_MASK_Rx

Same as INT_PENDING_Rx

R/W

•

Address: 0x78/0x79/0x7A/0x7B

•

Default: 0xFF

•

Description: Interrupt clear registers 1 to 4 (see Section 6.6.1).

Writing 0 unmasks the corresponding interrupt bit in INT_PENDING_Rx. These registers are reset to the default

value as long as RSTn is asserted.

For all bits:

0: interrupt is unmasked

1: interrupt is masked

6.6.8

Interrupt source registers (INT_SRC_Rx) (x = 1 to 4)

Table 77. INT_SRC_Rx

Same as INT_PENDING_Rx

•

Address: 0x7C/0x7D/0x7E/0x7F

•

Default: 0xXX (where X depends on the actual state of interrupt sources)

•

Description: Interrupt source registers 1 to 4 (see Section 6.6.1).

For all bits:

0: interrupt source is not present

1: interrupt source is present

6.6.9

Interrupt debug latch registers (INT_DBG_LATCH_Rx) (x = 1 to 4)

Table 78. INT_DBG_LATCH_Rx

Same as INT_PENDING_Rx

W/R0

•

Address: 0x80/0x81/0x82/0x83

•

Default: 0x00

•

Description: Interrupt debug latch registers 1 to 4 (see Section 6.6.1).

Setting a bit emulates the corresponding interrupt event. The bit is self-cleared, and always reads 0.

STPMIC25

DS14278 - Rev 3

page 108/145

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