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TMS320DM355 Datasheet(PDF) 112 Page - Texas Instruments

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Part # TMS320DM355
Description  Digital Media System-on-Chip (DMSoC)
PDF  153 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM355 Datasheet(HTML) 112 Page - Texas Instruments

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5.8 MMC/SD
5.8.1
MMC/SD Electrical Data/Timing
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
The DM355 includes two separate MMC/SD Controllers which are compliant with MMC V3.31, Secure
Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V1.0
specifications.
The MMC/SD Controller has following features:
• MultiMediaCard (MMC).
• Secure Digital (SD) Memory Card.
• MMC/SD protocol support.
• SDIO protocol support.
• Programmable clock frequency.
• 256 bit Read/Write FIFO to lower system overhead.
• Slave EDMA transfer capability.
The MMC/SD Controller does not support SPI mode.
Table 5-15. Timing Requirements for MMC/SD Module
(see Figure 5-20 and Figure 5-22)
DM355
NO.
FAST MODE
STANDARD MODE
UNIT
MIN
MAX
MIN
MAX
1
tsu(CMDV-CLKH)
Setup time, SD_CMD valid before SD_CLK high
6
5
ns
2
th(CLKH-CMDV)
Hold time, SD_CMD valid after SD_CLK high
2.5(1)
5
ns
3
tsu(DATV-CLKH)
Setup time, SD_DATx valid before SD_CLK high
6
5
ns
4
th(CLKH-DATV)
Hold time, SD_DATx valid after SD_CLK high
2.5
5
ns
(1)
For this parameter, you may include margin in your board design so that the toh = 2.5 ns of the MMC/SD device is not degraded at the
DM355 input pin.
Table 5-16. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 5-19 through Figure 5-22)
DM355
STANDARD
NO.
PARAMETER
FAST MODE
UNIT
MODE
MIN
MAX
MIN
MAX
7
f(CLK)
Operating frequency, SD_CLK
0
50
0
25
MHz
8
f(CLK_ID)
Identification mode frequency, SD_CLK
0
400
0
400
KHz
9
tW(CLKL)
Pulse width, SD_CLK low
7
10
ns
10
tW(CLKH)
Pulse width, SD_CLK high
7
10
ns
11
tr(CLK)
Rise time, SD_CLK
3
10
ns
12
tf(CLK)
Fall time, SD_CLK
3
10
ns
td(CLKL-
13
Delay time, SD_CLK low to SD_CMD transition
-7.5
4
-7.5
14
ns
CMD)
14
td(CLKL-DAT) Delay time, SD_CLK low to SD_DATx transition
-7.5
4
-7.5
14
ns
Peripheral Information and Electrical Specifications
112
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