AD82088 datasheet(30/84 Pages) ESMT

30 / 84 page

ESMT

AD82088

Elite Semiconductor Microelectronics Technology Inc.

Publication Date: Oct. 2022

Revision: 2.4

30/84

2C-Bus Transfer Protocol

 Introduction

AD82088 employs I

2C-bus transfer protocol. Two wires, serial data and serial clock carry information

between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can

operate as either a transmitter or a receiver. The master device initiates a data transfer and provides the

serial clock on the bus. AD82088 is always an I

2C slave device.

 Protocol



START and STOP condition

START is identified by a high to low transition of the SDA signal. A START condition must precede

any command for data transfer. A STOP is identified by a low to high transition of the SDA signal. A

STOP condition terminates communication between AD82088 and the master device on the bus. In

both START and STOP, the SCL is stable in the high state.



Data validity

The SDA signal must be stable during the high period of the clock. The high or low change of SDA only

occurs when SCL signal is low. AD82088 samples the SDA signal at the rising edge of SCL signal.



Device addressing

The master generates 7-bit address to recognize slave devices. When AD82088 receives 7-bit

address matched with 0110000 or 0110001 (

ERROR pin state during power up), AD82088 will

acknowledge at the 9

th bit (the 8th bit is for R/W bit). The bytes following the device identification

address are for AD82088 internal sub-addresses.



Data transferring

Each byte of SDA signaling must consist of 8 consecutive bits, and the byte is followed by an

acknowledge bit. Data is transferred with MSB first, as shown in the figure below. In both write and

read operations, AD82088 supports both single-byte and multi-byte transfers. Refer to the figure

below for detailed data-transferring protocol.

R/W

ACK

DEV_ADDR

SUB_ADDR

STOP

DATAIN

START

ACK

START

DEV_ADDR

SUB_ADDR

DEV_ADDR

DATAIN

STOP

R/W

ACK

START

DEV_ADDR

SUB_ADDR

DEV_ADDR

DATAIN

STOP

R/W

ACK

START

R/W

DATAIN

ACK

Byte

Write

Random

Address

Read

Sequential

Random

Read

START

DEV_ADDR

SUB_ADDR

DATAIN

STOP

R/W

ACK

Multi-Byte

Write

ACK

AD82088 Datasheet(PDF) 30 Page - Elite Semiconductor Memory Technology Inc.

AD82088 Datasheet(HTML) 30 Page - Elite Semiconductor Memory Technology Inc.

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