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AD82088 Datasheet(PDF) 37 Page - Elite Semiconductor Memory Technology Inc. |
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AD82088 Datasheet(HTML) 37 Page - Elite Semiconductor Memory Technology Inc. |
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37 / 84 page ![]() ESMT AD82088 Elite Semiconductor Microelectronics Technology Inc. Publication Date: Oct. 2022 Revision: 2.4 37/84 Address 0X01 : State control 2 AD82088 has a built-in PLL and supports multiple MCLK/Fs or BCLK/Fs ratios. If BCLK_SEL is high, the ratio is changed to BCLK/FS ratios. On the contrary, the ratio is changed to MCLK/FS ratios. Detail setting is shown in the following table. BIT NAME DESCRIPTION VALUE FUNCTION B[7] BCLK_SEL MCLK-less (BCLK system) 0 Disable 1 Enable B[6:5] FS[1:0] Sampling Frequency 00 32/44.1/48kHz 01 64/88.2/96kHz 1x 128/176.4/192kHz B[4] Reserved Multiple MCLK/FS or BCLK/FS ratio setting table BIT NAME DESCRIPTION VALUE B[6:5]=00 B[6:5]=01 B[6:5]=1x B[3:0] PMF[3:0] MCLK/Fs or BCLK/Fs Setup 0000 1024x 512x 256x 0001 Reset Default (64x) Reset Default (64x) Reset Default (64x) 0010 128x 128x 128x 0011 192x 192x 192x 0100 256x 256x 256x 0101 384x 384x Reserved 0110 512x 512x 0111 576x Reserved 1000 768x 1001 1024x |
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