AD82088 datasheet(72/84 Pages) ESMT

72 / 84 page

ESMT

AD82088

Elite Semiconductor Microelectronics Technology Inc.

Publication Date: Oct. 2022

Revision: 2.4

72/84

 Noise Gate Attack Level

When both left and right signals have 2048 consecutive sample points less than the programmable noise

gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8, x1/4, x1/2, or zero if

the noise gate function is enabled. Noise gate attack level is defined by 24-bit representation and is stored in

RAM address 0X5E of RAM bank 0.

 Noise Gate Release Level

After entering the noise gating status, the noise gain will be removed whenever AD82088 receives any input

signal that is more than the noise gate release level. Noise gate release level is defined by 24-bit

representation and is stored in RAM address 0X5F of RAM bank 0. The following table shows the noise gate

attack and release threshold level

’s numerical representation.

Sample calculation for noise gate attack and release level

Input amplitude

(dB)

Linear

Decimal

Hex

(1.23 format)

8388607

7FFFFF

-100

-5

-110

-5.5

L=10

(x/20)

D=8388607xL

H=dec2hex(D)

 DRC Energy Coefficient

x2[n]

DRC_EC

Z-1

xrms[n]

1-DRC_EC

The above figure illustrates the digital processing of calculating RMS signal power. In this processing, a DRC

energy coefficient is required, which can be programmed for different frequency range. Four sets of energy

coefficients are provided and used for respective DRC. Energy coefficient is defined by 24-bit representation

and is stored in RAM address 0X60, 0X61, 0X62, and 0X63 of RAM bank 0. The following table shows the DRC

energy coefficient numerical representation.

AD82088 Datasheet(PDF) 72 Page - Elite Semiconductor Memory Technology Inc.

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