PM4354-PI datasheet(39/463 Pages) PMC

39 / 463 page

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

Pin No. Function

CMVFPC

Input

Common H-MVIP Frame Pulse Clock (CMVFPC). The common H-MVIP

frame pulse clock provides the frame pulse clock for operation with 8.192

Mbit/s H-MVIP access.

CMVFPC is used to sample CMVFPB. CMVFPC is nominally a 50% duty

cycle clock with a frequency of 4.096 MHz. The falling edge of CMVFPC

must be aligned with the falling edge of CMV8MCLK with no more than

±10ns skew.

The Transmitter and Receiver streams are independently enabled for H-

MVIP access. When H-MVIP access is enabled, all four Transmitter (or

Receiver) streams are enabled for H-MVIP access. When both the

Transmitter and the Receiver H-MVIP accesses are disabled, CMVFPC is

unused.

Transmit Line Interface

TXTIP1[1]

TXTIP1[2]

TXTIP1[3]

TXTIP1[4]

TXTIP2[1]

TXTIP2[2]

TXTIP2[3]

TXTIP2[4]

Analog

Output

A13

R13

A11

T11

Transmit Analog Positive Pulse (TXTIP1[1:4] and TXTIP2[1:4]). When

the transmit analog line interface is enabled, the TXTIP1[x] and TXTIP2[x]

analog outputs drive the transmit line pulse signal through an external

matching transformer. Both TXTIP1[x] and TXTIP2[x] are normally

connected to the positive lead of the transformer primary. Two outputs are

provided for better signal integrity and must be shorted together on the

board.

After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The HIGHZ bit

of the quadrant’s XLPG Line Driver Configuration register (addresses 0F0H,

1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the high

impedance state.

TXRING1[1]

TXRING1[2]

TXRING1[3]

TXRING1[4]

TXRING2[1]

TXRING2[2]

TXRING2[3]

TXRING2[4]

Analog

Output

C13

T13

B11

R11

Transmit Analog Negative Pulse (TXRING1[1:4] and TXRING2[1:4]).

When the transmit analog line interface is enabled, the TXRING1[x] and

TXRING2[x] analog outputs drive the transmit line pulse signal through an

external matching transformer. Both TXRING1[x] and TXRING2[x] are

normally connected to the negative lead of the transformer primary. Two

outputs are provided for better signal integrity and must be shorted together

on the board.

After a reset, TXRING1[x] and TXRING2[x] are high impedance. The HIGHZ

bit of the quadrant’s XLPG Line Driver Configuration register (addresses

0F0H, 1F0H, 2F0H, 3F0H) must be programmed to logic 0 to remove the

high impedance state.

PM4354-PI Datasheet(PDF) 39 Page - PMC-Sierra, Inc

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