PM4354-PI datasheet(74/463 Pages) PMC

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PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

9.23 E1 Transmitter (E1-TRAN)

The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T

recommendations, providing individual enables for frame generation, CRC multiframe generation,

and channel associated signaling (CAS) multiframe generation.

In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides per-

timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of

the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle

code substitution and signaling substitution) by use of the master trunk conditioning bit in the

Configuration Register.

Common Channel Signaling (CCS) is supported in timeslot 16 through the Transmit Channel

Insertion (TXCI) block. Support is provided for the transmission of AIS and TS16 AIS, and the

transmission of remote alarm (RAI) and remote multiframe alarm signals.

The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword

registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may

individually carry data links sourced from the internal HDLC controller, or may be passed

transparently from the BTPCM[x] input.

9.24 T1 Inband Loopback Code Generator (XIBC)

The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback

codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous

repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled

to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the

code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the T1-

XBAS Basic Transmitter block.

9.25 Pulse Density Enforcer (XPDE)

The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is

enabled by a register bit within the XPDE.

This block monitors the digital output of the transmitter and detects when the stream is about to

violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density

violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure

the resultant output no longer violates the pulse density requirement. When the XPDE is disabled

from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.

9.26 T1 Signaling Aligner (SIGA)

When enabled, the Signaling Aligner is positioned in the backplane transmit path before the T1-

XBAS. Its purpose is to ensure that, if the signaling on BTSIG[x] is changed in the middle of a

superframe, the T1-XBAS completes transmitting the signalling bits (the A,B,C, and D bits in ESF

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