PM4354-PI datasheet(17/463 Pages) PMC

17 / 463 page

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

•

Uses line rate system clock.

•

Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan

test.

•

Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology.

•

Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.

•

Provides a -40°C to +85°C Industrial temperature operating range.

1.1

Receiver section:

•

Typical signal recovery of up to -43dB at 1024kHz (E1) and up to -44dB at 772kHz (T1/J1).

•

Guaranteed minimum signal recovery of -32dB at 1024kHz (E1) and -36dB at 772kHz (T1/J1).

•

Recovers clock and data using a digital phase locked loop for high jitter tolerance.

•

Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures

are consistent ITU-T G.706 specifications.

•

Frames to DSX/DS-1 signals in SF and ESF formats.

•

Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation

for Japanese applications. Frames in the presence of and detects the “Japanese Yellow” alarm.

•

Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and

Bellcore TR-TSY-000170.

•

Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window.

•

Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm

detection and integration are according to ANSI T1.231 specifications.

•

Provides programmable in-band loopback activate and deactivate code detection.

•

Supports line and path performance monitoring according to AT&T and ANSI specifications.

Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and

loss of frame or change of frame alignment events.

•

Provides performance monitoring counters sufficiently large as to allow performance monitor counter

polling at a minimum rate of once per second. Optionally, updates the performance monitoring

counters and interrupts the microprocessor once per second, timed to the receive line.

1 Based on actual results using PIC-22 gauge cable emulation. Refer to the COMET-QUAD Evaluator

Board for design recommendations (PMC-1991237).

PM4354-PI Datasheet(PDF) 17 Page - PMC-Sierra, Inc

PM4354-PI Datasheet(HTML) 17 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL