PM4354-PI datasheet(64/463 Pages) PMC

64 / 463 page

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

9.14 HDLC Receiver (RDLC)

The RDLC is a microprocessor peripheral used to receive HDLC frames on the T1 4kHz ESF

facility data link, the E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1).

The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros

on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check

sequence (FCS).

In the address matching mode, only those packets whose first data byte matches one of two

programmable bytes or the universal address (all ones) are stored in the FIFO. The two least

significant bits of the address comparison can be masked for LAPD SAPI matching.

Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a

programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are

detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.

The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt

status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status

FIFO. On end of message, the Status Register indicates the FCS status and if the packet

contained a non-integer number of bytes.

9.15 Bit Oriented Code Detector (RBOC)

The Bit Oriented Code detection function is provided by the RBOC block. This block detects the

presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link

channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194. The 64

code

(111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code

received.

Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting

of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when

repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has

been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the

RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two

code sequences containing code values different from the detected code are received in a moving

window of ten code periods.

Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all

ones (111111) if no valid code has been detected. An interrupt is generated to signal when a

detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits

go to all ones).

PM4354-PI Datasheet(PDF) 64 Page - PMC-Sierra, Inc

PM4354-PI Datasheet(HTML) 64 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL