PM4354-PI datasheet(83/463 Pages) PMC

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RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315

ISSUE 6

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE

NORMAL MODE REGISTER DESCRIPTION

Normal mode registers are used to configure and monitor the operation of the COMET-QUAD.

The Register Memory Map in Table 4 below shows where the normal mode registers are

accessed. The registers are organized so that backward software compatibility with existing PMC

devices is optimized. The COMET-QUAD contains 1 set of master configuration, H-MVIP, and

CSU registers and 4 sets of T1/E1 Framer registers. Where only 1 set is present, the registers

apply to the entire device. Where 4 sets are present, the registers apply to a single quadrant of

the COMET-QUAD. By convention, where 4 sets of registers are present, address space 000H –

0FFH applies to quadrant #1, 100H – 1FFH applies to quadrant #2, 200H – 2FFH applies to

quadrant #3, and 300H – 3FFH applies to quadrant #4.

On reset the COMET-QUAD defaults to T1 mode. For proper operation some register

configuration is expected. System side access defaults to the serial clock and data signals. By

default interrupts will not be enabled, and automatic alarm generation is disabled.

Notes on Normal Mode Register Bits:

1. Writing values into unused register bits has no effect. Reading back unused bits can produce

either a logic 1 or a logic 0; hence, unused register bits should be masked off by software

when read.

2. All configuration bits that can be written into can also be read back. This allows the processor

controlling the COMET-QUAD to determine the programming state of the chip.

3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted.

4. Writing into read-only normal mode register bit locations does not affect COMET-QUAD

operation unless otherwise noted.

5. Certain register bits are reserved. These bits are associated with functions that are unused in

this application. To ensure that the COMET-QUAD operates as intended, reserved register

bits must only be written with their default values unless otherwise stated. Similarly, writing to

reserved registers should be avoided unless otherwise stated.

10.1 Normal Mode Register Memory Map

Table 4 - Normal Mode Register Memory Map

Addr

000H

100H

200H

300H

Global Configuration

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