PM7347 datasheet(249/341 Pages) PMC

249 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

249

Document ID: PMC-1990267, Issue 3

Test Features Description

The test mode registers, shown in Table 27, are used for production and board testing.

During production testing, the test mode registers are used to apply test vectors. In this case, the

test mode registers (as opposed to the normal mode registers) are selected when A[10] is high.

During board testing, the digital output pins and the data bus are held in a high-impedance state

by simultaneously asserting (low) the CSB, RDB, and WRB inputs. All of the TSBs for the

S/UNI-JET are placed in test mode 0 so that device inputs may be read and device outputs may be

forced through the microprocessor interface. Refer to the section "Test Mode 0" for details.

Note: The S/UNI-JET supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port

that can be used for board testing. All digital device inputs may be read and all digital device

outputs may be forced through this JTAG test port.

Table 27 Test Mode Register Memory Map

Address

000H-3FFH

Normal Mode Registers

400H

Master Test Register

708H

SPLR Test Register 0

709H

SPLR Test Register 1

70AH

SPLR Test Register 2

70BH

Reserved

70CH

SPLT Test Register 0

70DH

SPLT Test Register 1

70EH

SPLT Test Register 2

70FH

SPLT Test Register 3

710H

PMON Test Register 0

711H

PMON Test Register 1

712H-71FH

Reserved

720H

CPPM Test Register 0

721H

CPPM Test Register 1

722H

CPPM Test Register 2

723H-72FH

Reserved

730H

DS3 FRMR Test Register 0

731H

DS3 FRMR Test Register 1

732H

DS3 FRMR Test Register 2

733H

DS3 FRMR Test Register 3

734H

DS3 TRAN Test Register 0

735H

DS3 TRAN Test Register 1

736H

DS3 TRAN Test Register 2

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