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PM7347 Datasheet(PDF) 169 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 169 Page - PMC-Sierra, Inc |
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169 / 341 page  S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 169 Document ID: PMC-1990267, Issue 3 Register 349H: J2-FRMR Error/Xbit Interrupt Status Bit Type Function Default Bit 7 R CRCEI X Bit 6 R FRMEI X Bit 5 R BPVI X Bit 4 R EXZI X Bit 3 R XBITI X Bit 2 R X3 X Bit 1 R X2 X Bit 0 R X1 X CRCEI The CRCEI bit is set to logic one if a failed CRC-5 check occurs. CRCEI is cleared when this register is read. FRMEI The FRMEI bit is set to logic one if an errored framing bit occurs. FRMEI is cleared when this register is read. BPVI The BPVI bit is set to logic one if a bipolar violation that is not part of a valid B8ZS code occurs (when UNI is logic zero in the J2-FRMR Configuration Register) or if a 0 to 1 transition is detected on RLCV (when UNI is logic one). BPVI is cleared when this register is read. EXZI The EXZI bit is set to logic one upon reception of eight-or-more consecutive zeroes. EXZI remains logic zero while UNI is set to logic one in the J2_FRMR Configuration Register. EXZI is cleared when this register is read. XBITI The XBITI bit is set to logic one if a change in the debounced (if XBIT_DEB is set to logic one) x-bits (X1, X2, and X3) is detected. XBITI is cleared when this register is read. |
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