PM7347 datasheet(172/341 Pages) PMC

172 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

172

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

PLDAIS

Bit 4

R/W

PHYAIS

Bit 3

R/W

DCRC

Bit 2

R/W

DLOS

Bit 1

R/W

DBPV

Bit 0

R/W

DFERR

The DFERR bit controls the insertion of framing alignment signal errors. When DFERR is set

to logic one, the framing alignment signal is inverted. When DFERR is set to logic zero, the

framing alignment signal is not inverted.

DBPV

The DBPV bit controls the insertion of single bipolar violations. When DBPV bit transitions

from 0 to 1, a violation is generated by masking the first violation pulse of a B8ZS signature.

To generate another violation, this bit must first be written to 0 and then to logic one again.

When DBPV is a logic zero, no violation is generated.

DLOS

When set to logic one, the DLOS bit forces the unipolar and bipolar outputs of the J2 TRAN

to be all zeros. When DLOS is logic zero, the outputs of the J2 TRAN operate normally.

DCRC

When set to logic one, a the CRC-5 check bits (e1-5) are inverted before transmission. DCRC

inverts the e1-5 bits even if CDIS of the J2 TRAN Configuration Register is set to logic one.

PHYAIS

When set to logic one, PHYAIS will cause the J2 TRAN to transmit an all 1's AIS (AIS).

PLDAIS

When set to logic one, PLDAIS will cause the J2 TRAN to insert all-ones in the payload data

bits. When PLDAIS is a logic zero, data is processed normally through the J2 TRAN.

PM7347 Datasheet(PDF) 172 Page - PMC-Sierra, Inc

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