PM7347 datasheet(178/341 Pages) PMC

178 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

178

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

Bit 6

OVR

Bit 5

COLS

Bit 4

PKIN

Bit 3

PBS[2]

Bit 2

PBS[1]

Bit 1

PBS[0]

Bit 0

INTR

Consecutive reads of the RDLC Status and Data Registers should not occur at rates greater than

1/10 that of the clock selected by the LINESYSCLK bit of the S/UNI-JET Miscellaneous

INTR

The interrupt (INTR) bit reflects the status of the internal RDLC interrupt. If the INTE bit in

the RDLC Interrupt Control Register is set to logic one, a RDLC interrupt (INTR is a logic

one) will cause INTB to be asserted low. The INTR register bit will be set to logic one when

one of the following conditions occurs:

• The number of bytes specified in the RDLC Interrupt Control Register are received on the

data link and are written into the FIFO.

• RDLC FIFO buffer overrun is detected.

• The last byte of a packet is written into the RDLC FIFO.

• The last byte of an aborted packet is written into the RDLC FIFO.

• Transition of receiving all-ones to receiving flags is detected.

PBS[2:0]

The packet byte status (PBS[2:0]) bits indicate the status of the data last

Read from the FIFO as indicated in Table 19:

Table 19 RDLC PBS[2:0] Data Status

PBS[2:0]

Data Status

000

The data byte read from the FIFO is not special.

001

The data byte read from the FIFO is the dummy byte that was written into the FIFO

when the first HDLC flag sequence (01111110) was detected. This indicates that the

data link became active.

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