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TMPR3927 Datasheet(PDF) 43 Page - Toshiba Semiconductor |
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TMPR3927 Datasheet(HTML) 43 Page - Toshiba Semiconductor |
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43 / 512 page  Chapter 1 Outline and Features 1-3 1.3 Features (1) TX39/H2 processor core • The TX39/H2 is a high-performance 32-bit microprocessor core Toshiba developed based on the R3000A architecture. • 8K bytes of instruction cache (2-way set associative) • 4K bytes of data cache (2-way set associative) • Supports burst refill and cache locking functions • Supports critical word first mode • MMU containing transition lookaside buffer (TLB) • Built-in hardware MAC unit for single-cycle DSP operation (throughput) • Built-in debug support unit (DSU) (2) SDRAM controller • 8 channels (6 channels shared with ROMC) • Supports SDRAM, DIMM flash, SGRAM, or SMROM memory • Supports 16M/64M/128M/256M-bit SDRAM with 2/4 bank size availability • Supports 16/32-bit data bus sizing on a per channel basis • Supports single data rate (SDR) SDRAM • Supports JEDEC standard 100-pin or 168-pin DIMM sockets for SDRAM • Supports JEDEC standard 100-pin DIMM sockets for flash memory • CKE-based timing control • Refresh control • Self-refreshing • 66 MHz clock (3) ROM Controller • 8 channels (6 channels shared with SDRAMC) • Supports ROM, page mode ROM, mask ROM, EPROM, E 2PROM, SRAM, and flash memory and I/O devices • Supports memory sizes of 1M byte to 1G byte in 32-bit mode, and sizes of 1M byte to 512M bytes in 16-bit mode. • Supports 16/32-bit data bus sizing on a per channel basis • Supports full speed (66 MHz max.)/half speed (33 MHz max.) bus mode • Supports selection between internal and external wait modes (ACK*/RDY) (4) Timers/Counters • 3-channel 24-bit up-counter • Supports interval timer mode, pulse generator mode, and watchdog timer mode (only for timer 2). • 2 timer output pins • Supports external input clock |
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