TMPR3927 datasheet(7/512 Pages) TOSHIBA

7 / 512 page

Table of Contents

12.5.2

Initiator Memory Read.......................................................................................................................12-91

12.5.3

Initiator Memory Write ......................................................................................................................12-92

12.5.4

Initiator I/O Read ...............................................................................................................................12-92

12.5.5

Initiator I/O Write ..............................................................................................................................12-93

12.5.6

Special Cycle .....................................................................................................................................12-93

12.5.7

Target Configuration Read .................................................................................................................12-94

12.5.8

8-word Burst Transfer from SDRAM to PCI .....................................................................................12-95

12.5.9

8-word Burst Transfer from PCI to SDRAM .....................................................................................12-96

13. Serial I/O Ports (SIO) ............................................................................................................................................13-1

13.1

Features.........................................................................................................................................................13-1

13.2

Block Diagram..............................................................................................................................................13-2

13.3

Registers .......................................................................................................................................................13-4

13.3.1

Register Map ........................................................................................................................................13-4

13.3.2

Line Control Registers (SILCRn) 0xFFFE_F300 (Ch. 0) 0xFFFE_F400 (Ch. 1)...............................13-5

13.3.3

DMA/Interrupt Control Registers (SIDICRn) 0xFFFE_F304 (Ch. 0) 0xFFFE_F404 (Ch. 1)...........13-7

13.3.4

DMA/Interrupt Status Registers (SIDISRn) 0xFFFE_F308 (Ch. 0) 0xFFFE_F408 (Ch. 1)..............13-9

13.3.5

Status Change Interrupt Status Registers (SISCISRn) 0xFFFE_F30C (Ch. 0)

0xFFFE_F40C (Ch. 1) .......................................................................................................................13-11

13.3.6

FIFO Control Registers (SIFCRn) 0xFFFE_F310 (Ch. 0) 0xFFFE_F410 (Ch. 1) ...........................13-12

13.3.7

Flow Control Registers (SIFLCRn) 0xFFFE_F314 (Ch. 0) 0xFFFE_F414 (Ch. 1) .........................13-13

13.3.8

Baud Rate Control Registers (SIBGRn) 0xFFFE_F318 (Ch. 0) 0xFFFE_F418 (Ch. 1)...................13-14

13.3.9

Transmit FIFO Registers (SITFIFOn) 0xFFFE_F31C (Ch. 0) 0xFFFE_F41C (Ch. 1).....................13-15

13.3.10 Receive FIFO Registers (SIRFIFOn) 0xFFFE_F320 (Ch. 0) 0xFFFE_F420 (Ch. 1) .......................13-16

13.4

Operation ....................................................................................................................................................13-17

13.4.1

Overview............................................................................................................................................13-17

13.4.2

Data Format .......................................................................................................................................13-17

13.4.3

Serial Clock Generator.......................................................................................................................13-19

13.4.4

Baud Rate Generator..........................................................................................................................13-19

13.4.5

Receive Controller .............................................................................................................................13-20

13.4.6

Receive Shift Register........................................................................................................................13-21

13.4.7

Receive Read Buffer ..........................................................................................................................13-21

13.4.8

Transmit Controller............................................................................................................................13-21

13.4.9

Transmit Shift Register ......................................................................................................................13-21

13.4.10 Host Interface.....................................................................................................................................13-21

13.4.11 Flow Controller ..................................................................................................................................13-22

13.4.12 Parity Controller.................................................................................................................................13-22

13.4.13 Error Flags .........................................................................................................................................13-22

13.4.14 Break Indication.................................................................................................................................13-23

13.4.15 Receive Timeout ................................................................................................................................13-23

13.4.16 Receive Data Transfer and the Handling of Receive FIFO Status Bits..............................................13-23

13.4.17 Multidrop System...............................................................................................................................13-24

13.4.18 Software Reset ...................................................................................................................................13-25

13.4.19 DMA Transfer Mode..........................................................................................................................13-25

13.5

Timing Diagrams ........................................................................................................................................13-26

13.5.1

Receiver Operation (7- and 8-bit Data Lengths) ................................................................................13-26

13.5.2

SITXDREQ*/SITXDACK and SIRXDREQ/SIRXDACK Timing for DMA Interface

(DMA Level 4) ..................................................................................................................................13-26

13.5.3

SITXDREQ*/SITXDACK and SIRXDREQ/SIRXDACK Timing for DMA Interface

(DMA Level 8) ..................................................................................................................................13-26

13.5.4

Receiver Operation (7- and 8-bit Lengths in Multidrop System Mode, RWUB = 1,

Waiting for an ID Frame) ...................................................................................................................13-27

13.5.5

Receiver Operation (7- and 8-bit Lengths in Multidrop System Mode, RWUB = 0,

Waiting for a Data Frame)..................................................................................................................13-27

13.5.6

Receiver Operation (7- and 8-bit Lengths in Multidrop System Mode, RWEB = 1,

Skipping Data Read) ..........................................................................................................................13-27

13.5.7

Transmitter Operation ........................................................................................................................13-28

13.5.8

Timing for Stopping Transmission by CTS* .....................................................................................13-28

14. Timer/Counter .......................................................................................................................................................14-1

TMPR3927 Datasheet(PDF) 7 Page - Toshiba Semiconductor

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