TMPR3927 datasheet(55/512 Pages) TOSHIBA

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Chapter 3 Pins

3-9

3.3

Pin Multiplexing

A total of 24 pins of the TX3927 have multiplexed functions. Table 3.3.1 shows the multiplexed pins.

The functions of individual pins are selected in different ways. Table 3.3.2 shows the pins for which the

PCFG control register determines the functions.

Table 3.3.1 Pin Multiplexing

Pin No.

Signal Name

Multiplexed Functions

217

SDCS_CE [5] *

SDCS [5] */CE [5] *

216

SDCS_CE [4] *

SDCS [4] */CE [4] *

215

SDCS_CE [3] *

SDCS [3] */CE [3] *

214

SDCS_CE [2] *

SDCS [2] */CE [2] *

GNT [0] *

GNT_0_OUT/GNT_IN

REQ [0] *

REQ_0_IN/REQ_OUT

REQ [1] *

REQ_1_IN/XINT_OUT

125

DMAREQ [3]

PIO [15] /DMAREQ [3] /TIMER [1]

126

DMAACK [3]

PIO [14] /DMAACK [3] /TIMER [0]

127

DMAREQ [2]

PIO [13] /DMAREQ [2] /TCLK

128

DMAACK [2]

PIO [12] /DMAACK [2]

220

DMAREQ [1]

PIO [11] /DMAREQ [1] /SDCS [7] */CE [7] *

219

DMAACK [1]

PIO [10] /DMAACK [1] /SDCS [6] */CE [6] *

129

DMAREQ [0]

PIO [9] /DMAREQ [0]

132

DMAACK [0]

PIO [8] /DMAACK [0]

133

DMADONE*

PIO [7] /DMADONE*/TIMER [0]

RXD [1]

PIO [6] /RXD [1]

TXD [1]

PIO [5] /TXD [1]

RXD [0]

PIO [4] /RXD [0]

TXD [0]

PIO [3] /TXD [0]

CTS [1] *

PIO [2] /CTS [1] */GSDAO [1]

RTS [1] *

PIO [1] /RTS [1] */DSF/GPCST [3]

CTS [0] *

INT [5] /CTS [0] *

RTS [0] *

INT [4] /RTS [0] *

The SDCS_CE[5:2]* chip select signals, corresponding to channels 5 to 2, respectively, are shared

for both SDRAM and ROM. If a given SDRAM or ROM channel is enabled using the SDRAM or

ROM controller, the corresponding pin is assigned to that channel. If SDRAM and ROM channels

having an identical number are enabled at the same time, the signal on the corresponding SDCS_CE pin

is asserted in both SDRAM and ROM bus cycles, resulting in undetermined memory data.

The PCI grant signals (GNT[3:0]*) and request signals (REQ[3:0]*) have different operations

depending on whether the chip booted into external or internal PCI arbiter mode. In internal arbiter

mode, REQ[3:0]* are input signals and GNT[3:0]* are output signals.

In external arbiter mode, REQ[0]* becomes a request signal output to the PCI module and GNT[0]*

becomes a grant signal input from the PCI module. REQ[1]* becomes an interrupt output that can be

controlled with the PIO module flag registers. REQ[3:2]* and GNT[3:1]*, which become output and

input pins, respectively, are not used.

TMPR3927 Datasheet(PDF) 55 Page - Toshiba Semiconductor

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