TMPR3927 datasheet(8/512 Pages) TOSHIBA

8 / 512 page

Table of Contents

14.1

Features.........................................................................................................................................................14-1

14.2

Block Diagram..............................................................................................................................................14-2

14.3

Registers .......................................................................................................................................................14-3

14.3.1

Register Map ........................................................................................................................................14-3

14.3.2

Timer Control Registers (TMTCRn) 0xFFFE_F000 (Ch. 0) 0xFFFE_F100 (Ch. 1)

0xFFFE_F200 (Ch. 2) ..........................................................................................................................14-4

14.3.3

Timer Interrupt Status Registers (TMTISRn) 0xFFFE_F004 (Ch. 0) 0xFFFE_F104 (Ch. 1)

0xFFFE_F204 (Ch. 2) ..........................................................................................................................14-5

14.3.4

Compare Registers A (TMCPRAn) 0xFFFE_F008 (Ch. 0) 0xFFFE_F108 (Ch. 1)

0xFFFE_F208 (Ch. 2) ..........................................................................................................................14-7

14.3.5

Compare Registers B (TMCPRBn) 0xFFFE_F00C (Ch. 0) 0xFFFE_F10C (Ch. 1)...........................14-8

14.3.6

Interval Timer Mode Registers (TMITMRn) 0xFFFE_F010 (Ch. 0) 0xFFFE_F110 (Ch. 1)

0xFFFE_F210 (Ch. 2) ..........................................................................................................................14-9

14.3.7

Clock Divider Registers (TMCCDRn) 0xFFFE_F020 (Ch. 0) 0xFFFE_F120 (Ch. 1)

0xFFFE_F220 (Ch. 2) ........................................................................................................................14-10

14.3.8

Pulse Generator Mode Registers (TMPGMRn) 0xFFFE_F030 (Ch. 0) 0xFFFE_F130 (Ch. 1) ......14-11

14.3.9

Timer Read Registers (TMTRRn) 0xFFFE_F0F0 (Ch. 0) 0xFFFE_F1F0 (Ch. 1)

0xFFFE_F2F0 (Ch. 2)........................................................................................................................14-12

14.3.10 Watchdog Timer Mode Register (TMWTMR2) 0xFFFE_F240 (Ch. 2) ............................................14-13

14.4

Operation ....................................................................................................................................................14-14

14.4.1

Interval Timer Mode ..........................................................................................................................14-14

14.4.2

Pulse Generator Mode........................................................................................................................14-16

14.4.3

Watchdog Timer Mode.......................................................................................................................14-17

14.5

Timing Diagrams ........................................................................................................................................14-19

14.5.1

Interrupt Timing in Interval Timer Mode...........................................................................................14-19

14.5.2

Output Flip-Flop Timing in Pulse Generator Mode ...........................................................................14-20

14.5.3

Interrupt Timing in Watchdog Timer Mode ......................................................................................14-20

15. Parallel I/O Port (PIO)...........................................................................................................................................15-1

15.1

Features.........................................................................................................................................................15-1

15.2

Registers .......................................................................................................................................................15-1

15.2.1

Register Map ........................................................................................................................................15-1

15.2.2

PIO Data Output Register (XPIODO) 0xFFFE_F500 .........................................................................15-2

15.2.3

PIO Data Input Register (XPIODI) 0xFFFE_F504..............................................................................15-3

15.2.4

PIO Direction Control Register (XPIODIR) 0xFFFE_F508................................................................15-4

15.2.5

PIO Open-Drain Control Register (XPIOOD) 0xFFFE_E50C ............................................................15-5

15.2.6

PIO Flag Register 0 (XPIOFLAG0) 0xFFFE_F510 ............................................................................15-6

15.2.7

PIO Flag Register 1 (XPIOFLAG1) 0xFFFE_F514 ............................................................................15-7

15.2.8

PIO Flag Polarity Control Register (XPIOPOL) 0xFFFE_F518 .........................................................15-8

15.2.9

PIO Interrupt Control Register (XPIOINT) 0xFFFE_F51C ................................................................15-9

15.2.10 CPU Interrupt Mask Register (XPIOMASKCPU) 0xFFFE_F520 ....................................................15-10

15.2.11 External Interrupt Mask Register (XPIOMASKEXT) 0xFFFE_F524...............................................15-11

15.3

Operation ....................................................................................................................................................15-12

15.3.1

Assigning PIO Pin Functions .............................................................................................................15-12

15.3.2

General-Purpose Parallel Port ............................................................................................................15-12

15.3.3

Interrupt Requests ..............................................................................................................................15-12

15.3.4

Accessing PIO Pins............................................................................................................................15-12

16. Power-On Sequence ..............................................................................................................................................16-1

17. Electrical Characteristics .......................................................................................................................................17-1

17.1

Absolute Maximum Ratings (*1) .................................................................................................................17-1

17.2

Recommended Operating Conditions (*2) ...................................................................................................17-1

17.3

DC Characteristics ........................................................................................................................................17-2

17.3.1

DC Characteristics – Non-PCI Interface Pins ......................................................................................17-2

17.3.2

DC Characteristics – PCI Interface Pins ..............................................................................................17-2

17.4

Crystal Oscillator Characteristics .................................................................................................................17-3

17.4.1

Recommended Oscillator Conditions (with a PLL Multiplication Factor of 16).................................17-3

17.4.2

Recommended Input Clock Conditions (with a PLL Multiplication Factor of 2)................................17-3

TMPR3927 Datasheet(PDF) 8 Page - Toshiba Semiconductor

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