TMPR3927 datasheet(96/512 Pages) TOSHIBA

96 / 512 page

Chapter 8 SDRAM Controller

8-12

8.4.6

SDRAM Command Register (SDCCMD) 0xFFFE_802C

Model Number

Version Number

: Type

0x20

0x10

: Initial value

SDCMSK

SDCMD

R/W

: Type

0x00

0x0

: Initial value

Bits

Mnemonic

Field Name

Description

31 : 24

Model Number

Model Number (initial value: 0x20)

Shows the model number.

The TX3927’s model number is 0x20. The field is read-only.

23 : 16

Version Number

Version Number (initial value: 0x10)

Shows the version number.

The TX3927’s version number is 0x10. The field is read-only.

11 : 4

SDCMSK

Channel Mask

Channel Mask (initial value: 0x00)

A “1” enables the command for the corresponding channel. The command is

executed in parallel on all enabled channels.

Bit 11: Channel 7

Bit 10: Channel 6

Bit 9: Channel 5

Bit 8: Channel 4

Bit 7: Channel 3

Bit 6: Channel 2

Bit 5: Channel 1

Bit 4: Channel 0

3 : 0

SDCMD

Command

Command (initial value: 0x0)

Selects the command for memory.

0x0: NOP command

0x1: Set the SDRAM/SGRAM mode register.

0x2: Set the SMROM mode register.

0x3: Precharge all SDRAM/SGRAM banks (PALL).

0x4: Enter low power mode.

0x5: Enter power-down mode.

0x6: Exit low power/power-down mode.

0x7-0xf: Reserved

Commands will only be executed on channels with a memory type of SDRAM,

SMROM, or SGRAM. Low power mode is self-refresh mode for SDRAMs/SGRAMs

and low power mode for SMROMs. Power-down mode is precharge power-down

mode for SDRAMs/SGRAMs and low power mode for SMROMs.

Note 1: The mask bits are also used for the SGRAM load mask and load color registers.

Any write cycle for the command register will wait until the command is executed. Therefore,

memory cycles cannot be executed until the command cycle is executed. The command cannot start

until the SDRAMC becomes idle.

First use the channel control register to enable the target channel before executing a command for the

channel. Commands will only be executed on channels enabled with the channel control register.

Figure 8.4.5 SDRAM Command Register

TMPR3927 Datasheet(PDF) 96 Page - Toshiba Semiconductor

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