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TMPR3927 Datasheet(PDF) 79 Page - Toshiba Semiconductor |
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TMPR3927 Datasheet(HTML) 79 Page - Toshiba Semiconductor |
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79 / 512 page  Chapter 6 Clocks 6-3 6.3.2 Register The power-down control register (PDCR) is used to control the power-down process. Bit 16 of this register is the power-down trigger bit (PDN), which is cleared to "0" by a reset. A subsequent transition from "0" to "1" will initiate the power-down sequence. The bit is not cleared automatically, so software must clear this bit before starting another power-down sequence. Bits [23:17] (PDNMSK[6:0]) contain a 7-bit mask for the interrupt input pins. Bit 17 masks external interrupt 0, bit 18 masks external interrupt 1, and so on. A "0" value in any mask bit prevents that interrupt pin from starting the power-up sequence while a "1" allows it. Bits [15:0] contain a value that determines the dominant delay between the PLL being enabled and the input clocks from the clock generator being activated. The total power- up delay is the sum of this value plus 24 XIN clock cycles. |
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