TMPR3927 datasheet(80/512 Pages) TOSHIBA

80 / 512 page

Chapter 6 Clocks

6-4

6.3.2.1

Power-Down Control Register (PDCR)

0xFFFE_E010

PDNMSK

PDN

R/W

: Type

0x7F

: Initial value

PUTCV

R/W

: Type

: Initial value

Bits

Mnemonic

Field Name

Description

23 : 17

PDNMSK [6 : 0]

Power-Down

Mask

Power Down Mask bit (initial value: 0x7F)

Specifies which external interrupt signals are used to terminate power-down mode.

A bit is allocated to each interrupt source. Setting 1 enables the corresponding

interrupt signal to terminate power-down mode.

PDNMSK [6]

= NMI

PDNMSK [5]

= INT [5]

PDNMSK [4]

= INT [4]

PDNMSK [3]

= INT [3]

PDNMSK [2]

= INT [2]

PDNMSK [1]

= INT [1]

PDNMSK [0]

= INT [0]

1: Enable interrupt.

0: Disable interrupt

PDN

Power-Down

Trigger

Power Down Trigger (initial value: 0)

This bit is a trigger for the power-down sequence. It is cleared to "0" upon reset and

a "0" to "1" transition will initiate the power-down sequence.

This bit does not clear to "0" automatically when power-down mode is terminated.

Clear the bit to "0" before starting a next power-down sequence.

15 : 0

PUTCV

Power-Up Time

Counter

Power Up Time Counter Value (initial value: 0x0000)

Specifies the delay between the PLL being enabled and the outputs of the clock

generator being enabled. The total wait time is this value plus 3.5 XIN clock cycles.

Ensure that the power-up sequence is performed when the XIN clock is stable. XIN

can be 1/16 or 1/2 of the CPU core clock depending on the selected PLL multiplier

value.

Note:

For the bits other than those defined above, write the values shown in the figure.

Figure 6.3.1 Power-Down Control Register

TMPR3927 Datasheet(PDF) 80 Page - Toshiba Semiconductor

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