TMPR3927 datasheet(86/512 Pages) TOSHIBA

86 / 512 page

Chapter 8 SDRAM Controller

8-2

vice-versa might produce unpredictable results possibly including a bus hang.

(14) Arbitrary byte write for single or burst writes. This feature is controlled with the BWE signal.

(15) Premature termination of an internal bus cycle with a bus error or GDRESET* will allow memory

operation to complete with no loss of data. Termination of an internal bus cycle with RESET* will,

however, terminate memory operation immediately.

(16) Programmable refresh period

(17) SDRAM/SGRAM refresh mode: Auto refresh or self-refresh

(18) Low power modes: Self-refresh or precharge power-down for SDRAM/SGRAM and low power mode

for SMROM. Automatic exit from the power-down modes is supported.

(19) Addressing mode: Sequential only

(20) Auto precharge is used for burst writes only. Precharge commands are used for other types of access.

(21) Serial Presence Detect (SPD) to determine the configuration of DIMMs may be implemented by using

two programmable I/O (PIO) pins. The user should implement the serial protocol through software.

(22) High fanout

In order to support additional loading on the data bus, two selectable data read-back paths and an

optional slow write burst mode are supported. For reads, the user can choose between the path where

data is latched using a feedback clock to better maintain timing coherency with the data and the path

that bypasses that latching stage. For slow burst writes, two clocks are used for each write instead of

one.

(23) SDR (Single Data Rate) SDRAMs/SGRAMs are supported. DDR (Double Data Rate) devices are not

supported.

TMPR3927 Datasheet(PDF) 86 Page - Toshiba Semiconductor