 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMPR3927 Datasheet(PDF) 92 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMPR3927 Datasheet(HTML) 92 Page - Toshiba Semiconductor |
|
|
92 / 512 page  Chapter 8 SDRAM Controller 8-8 8.4.3 SDRAM Timing Register 1 (for SDRAM/SGRAM) (SDCTR1) 0xFFFE_8020 31 29 28 27 26 25 24 23 18 17 16 SDBC SDACP SDP SDCD WRT SDRC CASL DRB R/W R/W R/W R/W R/W R/W R/W R/W : Type 0000 0 0 000000 0 0 00 : Initial value 15 14 13 12 11 0 0SWB BW WpB SDRP R/W R/W R/W R/W : Type 0 0 0 0x400 : Initial value Bits Mnemonic Field Name Description 31 : 29 SDBC Bank Cycle Time Bank Cycle Time (tRC) (initial value: 000) Selects the bank cycle time for memory. 000: 5 tCK (reset) 100: 9 tCK 001: 6 tCK 101: 10 tCK 010: 7 tCK 110: Reserved 011: 8 tCK 111: Reserved 28 : 27 SDACP Active Command Period Active Command Period (tRAS) (initial value: 00) Selects the active command period for memory. 00: 3 tCK (reset) 01: 4 tCK 10: 5 tCK 11: 6 tCK 26 SDP Precharge Time Precharge Time (tRP) (initial value: 0) Select the precharge time for memory. 0: 2 tCK (reset) 1: 3 tCK 25 SDCD RAS-CAS Delay RAS to CAS Delay (tRCD) (initial value: 0) 0: 2 tCK (reset) 1: 3 tCK 24 WRT Write Recovery Time Write Recovery Time (tWR) (initial value: 0) Selects the write recovery time for memory. 0: 1 tCK (reset) 1: 2 tCK 23 : 18 SDRC Refresh Counter Refresh Counter (initial value: 000000) Decremented at each refresh. When the refresh circuit is activated with a non-zero value loaded, this field functions as a down-counter which stops at 0. A non-zero value must be reloaded to begin another countdown. Used for memory initialization. 17 CASL CAS Latency CAS Latency (tCASL) (initial value: 0) Selects the CAS latency. 0: 2 tCK (reset) 1: 3 tCK 16 DRB Data Read Bypass Data Read Bypass (initial value: 0) Selects which data read-back path is used. 0: Use the feedback clock to latch data into the register (reset). 1: Bypass the data latching stage. Figure 8.4.2 SDRAM Timing Register 1 (for SDRAM/SGRAM) (1/2) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
