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TMPR3927 Datasheet(PDF) 91 Page - Toshiba Semiconductor

Part # TMPR3927
Description  32-Bit TX System RISC TX39 Family
PDF  512 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3927 Datasheet(HTML) 91 Page - Toshiba Semiconductor

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Chapter 8 SDRAM Controller
8-7
Bits
Mnemonic
Field Name
Description
2 : 1
SDCS
1
Column Size
Column Size (initial value: 00)
Selects the column size of memory.
00: 256 words (8-bit)
01: 512 words (9-bit)
10: 1024 words (10-bit)
11: 2048 words (11-bit)
0SDMW
2
Memory Width
Memory Width (initial value: 0)
Selects the memory bus width.
0: 32-bit
1: 16-bit
Note 1: These fields are used for SDRAMs or SGRAMs only. They are ignored for all other memory types.
Note 2: The memory width field should always be set to 0 for SMROM or SGRAM.
Figure 8.4.1 SDRAM Channel Control Registers (2/2)
•
Note on using the base address (SDBA) and address mask (SDAM)
The address mask (SDAM) specifies whether the corresponding address bits of the base address (SDBA)
are used to determine the address space for the channel. Note that the address space can only be allocated
within specified boundaries. For example, the following setting allocates the address space in the range of
0xA000_0000 to 0xA1FF_FFFF, instead of 0xA100_0000 to 0xA2FF_FFFF.
Example:
SDCCR: 0x010301ea
-SDBA
= 0000 0001 000b
-SDAM
= 0000 0001 111b
Mask these address bits



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