TMPR3927 datasheet(70/512 Pages) TOSHIBA

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Chapter 5 Configuration

5-2

Bits

Mnemonic

Field Name

Description

PSNP

PCI Snoop

PCI Bus Request Snoop

Enables or disables the TX39/H2 core cache snoop function while the PCI has bus

mastership. If data cache is used in write back mode, the snoop function must be

disabled.

0: Disable the cache snoop function.

1: Enable the cache snoop function.

PPRI

PCI Arbitration

Priority

Select PCI Arbitration Priority

Specifies the priority of the DMAC to PCI.

0: DMA has priority over PCI in arbitration.

1: Setting prohibited.

5 : 4

PLLM

PLL Multiplier

Indicates the PLL multiplier value. Latched from ADDR[3:2] during a reset.

When PLLM[1] is set to “1”, a crystal having a frequency in the range of 6.25 to 8.33

MHz should be used.

When PLLM[1] is set to “0”, a crystal oscillator should be used and connected to the

XIN pin as a clock input signal. The XOUT pin should be left open.

00: Don’t use.

01:

×2

10: Don’t use.s

11:

×16

ENDIAN

Endian

Current Endian Setting of G-Bus

Indicates the endian mode. Latched from ADDR[14] during a reset.

0: Little endian

1: Big endian

The setting of this bit is not affected by the state of the RE (reverse endian) bit of

the TX39/H2 core status register.

HALF

Half-Speed

System Clock Half-Speed Mode

Indicates the SYSCLK output frequency.

The state of this bit is determined from the values of ADDR[15] and ADDR[9:8]

during a reset.

Half speed mode is selected when ADDR[15] is “0” or when ADDR[9:8] is “10”.

Otherwise, full speed mode is selected.

0: Full speed (same frequency as G-Bus clock frequency)

1: Half speed (half of G-Bus clock frequency)

ACEHOLD

ACE Hold

ACE* Address Hold

Specifies whether the address is held for one clock cycle after ACE* is deasserted.

0: The address changes in the same clock cycle as ACE*. In this mode, an address

hold time of 1 ns is guaranteed.

1: The address is held for one clock cycle after the rising edge of ACE*.

Note:

For the bits other than those defined above, write the values shown in the figure.

Figure 5.1.1 Chip Configuration Register (2/2)

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