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TMPR4937 Datasheet(PDF) 384 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 384 Page - Toshiba Semiconductor |
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384 / 552 page  Chapter 11 Serial I/O Port 11-24 11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller. • Little Endian: 0xF320 (Ch.0), 0xF420 (Ch.1) • Big Endian: 0xF323 (Ch.0), 0xF423 (Ch.1) 31 16 Reserved : Type : Initial value 15 8 7 0 Reserved RxD R : Type Undefined : Initial value Bit Mnemonic Field Name Description Read/Write 31:8 Reserved ⎯ 7:0 RxD Reception Data Receive Data This field reads reception data from the Receive FIFO. Reading this register updates the Reception Data Status. R Figure 11.4.9 Receive FIFO Register |
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