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TMPR4937 Datasheet(PDF) 118 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 118 Page - Toshiba Semiconductor |
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118 / 552 page  Chapter 7 External Bus Controller 7-18 7.3.7.5 Ready Input Timing The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK* input timing explained in 7.3.7.4 ACK* Input Timing (External ACK Mode) with the two following exceptions. • Ready must be a High Active signal. • When in the Ready mode, the Wait cycle count specified by EBCCRn.PWT:WT must be inserted in order to delay the Ready signal check (see 7.3.6.3 Ready Mode). Figure 7.3.13 Ready Input Timing (Read Cycle) SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) Latch Data Acknowledge Ready 2 clocks EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 ACK*/READY (Input) 2 clocks SYSCLK CE* ADDR [19:0] OE* DATA [31:0] Latch Data Acknowledge Ready EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Start Ready Check |
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